The present invention relates to event signalling systems and methods for digital signal processor systems. More particularly, the present invention relates to systems and methods for signalling the occurrence of events to one or more computing processors, where data flow into and out of a digital signal processor system is substantially through a data RAM and is independent of the one or more computing processors.
Digital signal processing has evolved from being an expensive, esoteric science used primarily in military applications such as radar systems, image recognition, and the like, to a high growth technology which is used in consumer products such as digital audio and the compact disk. Single chip digital signal processors (SCDSPs) were introduced in the early 1980's to specifically address these markets. However, SCDSPs are complex to design and use, and have significant development, environment, and performance limitations which stem from their Von Neuman, microprocessor origins. In particular, while the requirements of signal processing are that the signal processor be computationally intensive and controllable, have low latency and low parasitic overhead for real time I/O, and be able to efficiently execute multiple asynchronous processes, the signal processors of the art are burdened with the interrupt structures and the memory intensiveness of their microprocessor ancestors. The interrupt structures found in the SCDSPs of the art typically result in the SCDSPs being limited to a frequency spectrum from DC to the low tens of KHz.
In overcoming the problems of the SCDSPs of the art, a digital signal processor (also referred to as a "SPROC") architecture was set forth in parent application Ser. No. 07/525,977 filed May 18, 1990, now abandoned and continued as co-ending application Ser. No. 07/900,536 filed Jun. 18, 1992, where the interrupt structure and tasks are substantially removed from the tasks of the computing processor(s) (e.g. the GSPs). The separation is achieved by providing a central memory unit (data RAM) through which flows substantially all the data coming into and out of the signal processor, and by providing a data flow manager (i.e. a data I/O processor) which handles I/O between the central memory unit and the "outside" world. The computing processor(s) is coupled to the central memory unit and does not communicate directly with the outside world. Where multiple computing processors are utilized, the multiple processors do not communicate directly; rather they communicate via the central memory unit. However, even though the computing processors are shielded from the I/O functions of the SCDSP and are therefore capable of increased throughput, a mechanism for informing (signalling) the computing processors of events of interest such as the availability of desired information must be provided.